Arithmetic Unit Implementation Using Delay Optimized Vedic Multiplier with Bist Capability

The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip. Still the load on the processor is not less in generic system. This load is reduced by supplementing the main processor with Co-Processors, which are designed to work upon specific type of functions like numeric computation, Signal Processing, Graphics etc. in which the Arithmetic Unit is most dominant Co-Processor which perform Arithmetic operations like addition, subtraction, multiplication and division. Without these operations which are performed by Arithmetic Unit no Technology can exist in real world. Faster Operations are of extreme importance in Arithmetic Unit. The speed of Arithmetic Unit depends greatly on the multiplier. ; Therefore, engineers are constantly looking for new algorithms and hardware to implement this operation in much optimized way in the terms of area and speed. In algorithmic and structural levels, numerous multiplication techniques have been developed to enhance the efficiency of the multiplier which concentrates in reducing the partial products and the methods of their addition but the principle behind multiplication remains the same in all cases. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. Employing these techniques in the computation algorithms of the coprocessor will reduce the complexity, execution time, area etc. Though there are many sutras employed to handle different sets of numeric, exploring each one gives new results. Our work has proved the efficiency of Urdhva Triyakbhyam-Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of intermed Urdhvaiate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm with processors, the compatibility to different data types. This Sutra was traditionally used in ancient India for the multiplication of two decimal numbers in relatively less time. In this paper, after a gentle introduction of this Sutra, it is applied to the binary number system to make it useful in the digital hardware. The hardware architecture of the Vedic multiplier is presented and is shown to be very similar to that of the popular array multiplier. We have seen that much delay is consumed by the conventional adders which are used to generate the partial products so we have further optimized the Vedic multiplier “Urdhva Triyakbhyam” algorithm by replacing the conventional adder with the Carry save Adder to achieve further Delay Optimization. The proposed design show improvement of speed over the conventional designs and then the result achieved by the proposed method has been compared by Karatsuba Multiplier. After the presentation of the Vedic multiplier in this paper we have used it for the implementation of Arithmetic unit using optimized Vedic Multiplier which is not only useful for the optimizing the arithmetic unit of ALU but also is useful in the field of digital signal processing directly as we have put area and delay optimized MAC unit in our module of arithmetic unit. The proposed Arithmetic unit is coded in Verilog HDL, synthesized and simulated using Xilinx software. The Arithmetic Unit is implemented on a FPGA device Spartan XC3S500-5-FG320 using Xilinx tool. Finally, the implemented design has been tested by using Built in Self-Test, which shows that this Arithmetic unit is completely fault free.